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Ge NC-GAAFETs: SCE Reduction, Switch Speed, Synaptic Applications

发布日期:2019-03-07 浏览量:2

专用集成电路与系统国家重点实验室

讲座信息


Presenter: Peide Ye, Purdue University

Date: 2019/03/15, 9:00AM

Location:微电子楼B213

Title: Ge NC-GAAFETs: SCE Reduction, Switch Speed, Synaptic Applications

Abstract:

The so-called Boltzmann Tyranny defines the fundamental thermionic limit of the subthreshold slope (SS) of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV/dec at room temperature and, therefore, precludes the lowering of the supply voltage and the overall power consumption. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier. We apply Ge gate-all-around (GAA) nanowire MOSFETs as the test vehicles integrated with ferroelectric Hf0.5Zr0.5O2 (HZO) gate dielectric and demonstrate bi-dimensional sub-60 mV/dec operations. [1] Negative capacitance (NC) effect can further reduce the short-channel effect and improve the off-state performance of these Ge GAAFETs. [2] By ultra-fast pulse measurements, it is found that HZO could switch its polarization directly by a single pulse with the minimum pulse width of 3.6 ns. The polarization switching triggered by pulse train with pulse width as short as 100 ps is also demonstrated for the first time. [3] Finally, we also demonstrate to use Ge ferroelectric nanowire FET as synaptic device for online learning in neural network with high number of conductance state and Gmax/Gmin. [4] The work is in close collaborations with Wonil Chung, Mengwei Si, Pragya R. Shrestha, Jason P. Campbell, and Kin P. Cheung.
References:
[1] W. Chung et al., IEDM., p. 365, 2017.
[2] W. Chung et al., DRC, 2018.
[3] W. Chung et al., VLSI, p. 89, 2018.
[4] W. Chung et al., IEDM, 2018.

Bio:

Dr. Peide Ye is the Richard J. and Mary Jo Schwartz Professor of Electrical and Computer Engineering at Purdue University. He received BS from Fudan University, China in 1988 and Ph.D. from Max-Planck-Institute of Solid State Research, Germany, in 1996. Before joining the Purdue faculty in 2005, he worked for NTT Basic Research Laboratory, NHMFL/Princeton University, and Bell Labs/Lucent Technologies/Agere Systems. His current research work is focused on atomic layer deposition technology and its device integration on novel channel materials including III-V, Ge, 2D materials and complex oxides. He authored and co-authored more than 200 peer-reviewed articles and 350 conference presentations including many invited, keynote and plenary talks. He also served as chairmen and program committee members on top international conferences and symposia. He received various fellowships and awards such as Volkswagen, Max-Planck Society, NTT fellowships and IBM faculty, Sigma Xi Research and Arden Bement Jr. awards. He is Fellow of IEEE and APS (American Physical Society).

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