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Effective and Practical Techniques for Design, Testing, and Built-in Self-Test and Self-Calibration of Analog and Mixed-Signal Integrated Circuits

发布日期:2018-12-03 浏览量:103

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讲座信息


时间:2018年12月5日周三上午9:30

地点:张江校区微电子楼369会议室 

Title: 

Effective and Practical Techniques for Design, Testing, and Built-in Self-Test and Self-Calibration of Analog and Mixed-Signal Integrated Circuits

Speaker: 

Degang Chen(陈德刚), Professor/IEEE Fellow 

Jerry Junkins Chair in the College of Engineering 

Director of Analog and Mixed-Signal VLSI Center 

Chair of College of Engineering Promotion and Tenure Committee 

Dept of Electrical and Computer Engineering 

Iowa State University, Ames, IA 50011 

(515)294-6277, djchen@iastate.edu


Abstract: 

As semiconductor technology advances into a new era of Internet of Things, increasingly more development emphasis is being placed on interface circuits and increasingly more analog and mixed-signal functions are deeply embedded in complex ICs. On one hand, customers and system integrators demand higher and higher circuit performance; on the other hand, low-cost pressure keeps shrinking the resources available for achieving such performance. Furthermore, many important applications such as automotive electronics pose stringent requirements on reliability and functional safety, pushing for tests and more stringent tests.  

In this talk, we will briefly review some recent analog design techniques for cost-effective enhancement of analog and mixed-signal circuit performance, for ultra-small and high linearity temperature sensors and current sensors, which are critical for power, thermal and reliability management. We will then focus on some effective and practical techniques for innovative testing, BIST, and BIST-based self-calibration of analog to digital converters. In particular, we will describe several techniques to: 1) reduce test data acquisition time by >100X while maintaining or even improving test quality, 2) relax the test signal’s linearity requirement by hundreds to thousands of times without affecting test accuracy, 3) significantly reduce the clock jitter requirements, and/or 4) implement the relaxed test methods as BIST solutions for BIST-based calibration. Most of the results are validated at industry labs or productions tests at Texas Instruments, NXP, and Maxim


Short Bio: 

Degang Chen received his BS degree in instrumentation and automation from Tsinghua University, China, in 1984 and his PhD degree in control theory from UC Santa Barbara, CA, USA, in 1992.  

He was the John R. Pierce Instructor at CalTech in 1992. After that, he joined Iowa State University where he is currently Professor of Electrical Engineering and the Jerry Junkins Chair in the College Engineering. His industry experience includes Beijing Institute of Control Engineering in 1984-1986, the Boeing Company in 1999 summer, Maxim Integrated in 2001 summer, and Texas Instruments in 2011, 2012 and 2014 summers. His current research interests are in analog and mixed-signal IC design and testing, integrated sensor design, analog verification, and built-in self-test self-calibration for enhancing performance and reliability. 

Dr. Chen has authored and co-authored 8 patents and over 280 refereed publications in leading journals and top international conferences. Of those, 15 received best paper awards and other honors, including the prestigious IEEE Ned Kornfield Best Paper Award in 2013 and again in 2014. He has frequently delivered technical seminars at most leading semiconductor companies such as Texas Instruments, Intel, Broadcom, Qualcomm, IBM, Infineon, NVidia, Xilinx, etc., as well as at various universities. 

Dr. Chen is a Fellow of the IEEE, and is an IEEE Instrumentation and Measurement Society Distinguished Lecturer.