研究方向：

面向5G/6G/卫星通信的高速毫米波集成电路与系统

相控阵技术调幅调相射频组件及收发机系统

超低功耗毫米波收发机架构与芯片设计

教育背景：

2014年 – 2019年日本东京工业大学，电子物理学，博士

2011年 – 2014年电子科技大学，电磁场与微波技术，硕士

2012年 – 2013年韩国浦项工业大学，微电子，硕士交换

2007年 – 2011年电子科技大学，电磁场与无线技术，学士

工作学术经历：

2022年 - 至今复旦大学微电子学院，青年研究员

2019年 - 2021年日本东京工业大学工学院，研究员

获奖或荣誉：

Seiichi Tejima 学术研究奖，2021

IEEE RFIC Symposium 会议最佳论文奖，2019

IEICE Transaction on Electronics 期刊最佳论文奖，2018

IEEE Symposia on VLSI 会议推荐论文，2017

项目：

国家自然科学基金青年科学基金项目，主持

代表性成果：

1. Yunhao Li, Yun Wang, Sicheng Han, Ziyang Deng, Wen Zuo, Wei Li, Yue Lin, Hongtao Xu, “A 1.5-to-23.5 GHz High-Power-Density Distributed PA Achieving 150.5 Gb/s Data Rate With 14.4 dBm Pavg Supporting 64/128/256-QAM in 40-nm CMOS, IEEE ESSERC(ESSCIRC), Bruges, Belgium, Sep. 2024.

2. Wen Zuo, Yun Wang, Sicheng Han, Yunhao Li, Wei Li, Yue Lin, Hongtao Xu, “A PVT-Robust 2.4-GHz-BW 59.7-dB-Range 0.39-dB-Error dB-Linear VGA with Self-Compensated Exponential Generator and Self-Adaptive Bias, IEEE ESSERC(ESSCIRC), Bruges, Belgium, Sep. 2024.

3. Sicheng Han, Yun Wang, Yunhao Li, Wen Zuo, Wei Li, Yue Lin, Hongtao Xu, “A 140-Gbps 1-to-21-GHz Ultra-Wideband LNA Achieving 1.95-to-3-dB NF Using Gm-Assisted-Feedback Noise Suppression Technique in 40nm Bulk CMOS, IEEE Symposium on VLSI Circuits (VLSI), Honolulu, Hawaii, USA, June 2024.

4. Chunhui Fang, Yun Wang, Chenchen Yang, Tong Li, Yong Chen, Yue Lin, Hongtao Xu, “A 22.5-33.5GHz Hybrid Phase Shifter With Low Phase and Amplitude Error for 5G and Satellite Communication, IEEE TMTT, 2024.

5. Xi Fu, Dongwon You, Yun Wang, Xiaolin Wang, Ashibir Aviat Fadila, Chenxin Liu, Sena Kato, Chun Wang, Zheng Li, Jian Pang, Atsushi Shirane, and Kenichi Okada, “A Low-Power Radiation-Hardened Ka-Band CMOS Phased-Array Receiver for Small Satellite Constellation”, IEEE JSSC, 2023.

6. Xi Fu, Dongwon You, Xiaolin Wang, Yun Wang, et al., “A Low-Power 256-Element K a-Band CMOS Phased-Array Receiver With On-Chip Distributed Radiation Sensors for Small Satellite Constellations”, IEEE JSSC, 2023.

7. Yun Wang, et al., “A Ka-Band SATCOM Transceiver in 65-nm CMOS with High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Terminal”, IEEE JSSC, 2022

8. Xi Fu, Yun Wang, et al., “A 3.4mW/element Radiation-Hardened Ka-Band CMOS Phased-Array Receiver Utilizing Magnetic-Tuning Phase Shifter for Small Satellite Constellation”, IEEE ISSCC, 2022.

9. Dongwon You, Yun Wang, et al., “A Ka-Band Dual Circularly Polarized CMOS Transmitter with Adaptive Scan Impedance Tuner and Active XPD Calibration Technique for Satellite Terminal”, IEEE RFIC, 2022.

10. Dongwon You, Yun Wang, et al., IEEE ISSCC Student Research Preview, San Francisco, CA, Feb. 2022.

11. Xi Fu, Yun Wang, et al., “A CMOS SPDT RF Switch with 68-dB Isolation and 1.0-dB Loss Feathering Switched Resonance Network for MIMO Applications”, IEICE Transactions on Electronics, Jul. 2021.

12. Junjun Qiu, Zheng Sun, Bangan Liu, Wenqian Wang, Dingxin Xu, Hans Herdian, Hongye Huang, Yuncheng, Zhang, Yun Wang, Atsushi Shirane, Kenichi Okada, “A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth, IEEE ISSCC, 2021.

13. Atsushi Shirane, Yun Wang, and Kenichi Okada, A CMOS Ka-Band Wireless Transceiver for Future Non-Terrestrial 6G Networks,(invited) IEEE ICSICT, Kunming, China, Nov. 2020.

14. Yun Wang, et al., “A CMOS Ka-Band SATCOM Transceiver with ACI-Cancellation Enhanced Dual-Channel Low-NF High-Dynamic-Range RX and High-Linearity TX”, 2020 IEEE RFIC, Los Angeles, CA, June 2020.

15. Xi Fu, Yun Wang, et al., “A 68-dB Isolation 1.0-dB Loss Compact CMOS SPDT RF Switch Utilizing Switched Resonance Network”, IEEE MTT-S IMS, Los Angeles, CA, June 2020.

16. Yun Wang, et al., “A 39-GHz 64-Element Phased-Array Transceiver with Built-in Phase and Amplitude Calibration for Large-Array 5G NR in 65-nm CMOS”, IEEE JSSC, 2020.

17. Yun Wang, et al., “A 39GHz Phased-Array CMOS Transceiver with Built-in Calibration for Large-Array 5G NR”, 2019 IEEE RFIC, Boston, MA, June 2019.

18. Yun Wang, et al., “A 60-GHz 3.0Gb/s Spectrum Efficient BPOOK Transceiver for Low-power Short-range Wireless in 65-nm CMOS”, IEEE JSSC, 2019.

19. Haosheng Zhang, Aravind Tharayil Narayanan, Hans Herdian, Bangan Liu, Yun Wang, Atsushi Shirane, and Kenichi Okada, 0.2mW 70fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur, IEEE Symposium on VLSI Circuits (VLSI), Kyoto, Japan, June 2019.

20. Jian Pang, Rui Wu, Yun Wang, et al., “A 28GHz CMOS Phased-Array Transceiver Based on LO Phase Shifting Architecture with Gain Invariant Phase Tuning for 5G New Radio”, IEEE JSSC, 2019; RFIC, 2018.

21. Yun Wang, et al., 2019 ISSCC Student Research Preview, San Francisco, CA, Feb. 2019.

22. Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, and Kenichi Okada, “A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Sub-sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS, IEEE JSSC, 2019; ISSCC 2019.

23. Jian Pang, Zheng Li, Ryo Kubozoe, Xueting Luo, Rui Wu, Yun Wang , et al., “A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR, IEEE JSSC, 2020; ISSCC 2019.

24. Yun Wang, et al, A Compact 39-GHz 17.2-dBm Power Amplifier for 5G Communication in 65-nm CMOS, IEEE RFIT, Melbourne, Australia, Aug. 2018.

25. Bangan Liu, Yun Wang, et al., “A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS”, IEICE Trans. on Electronics, Feb. 2018.

26. Yun Wang, et al., “A 20-GHz Differential Push-Push VCO for 60-GHz Frequency Synthesizer toward 256QAM Wireless Transmission in 65-nm CMOS”, IEICE Transaction on Electronics, June 2017.