欢迎本科生、硕博研究生、博士后加入课题组。提供全面的芯片开发环境，包括设计、流片、测试等关键流程。给予系统性的学术训练以及良好融洽的团队氛围。有兴趣者请邮件联系。

研究方向：

1、面向关键安全型应用的高可靠智能算法与专用加速芯片：

　　此方向专注于研究适用于关键安全型应用的高可靠智能算法及其芯片实现。研究内容涵盖星上智能处理、自动驾驶系统、机器人控制技术等多个领域。通过构建高度可靠的算法和芯片，致力于提升关键应用的安全性和智能化水平，确保关键系统的稳定运行和数据安全。

2、面向商业航天低成本要求的集成电路加固技术：

　　该研究方向聚焦于商业航天领域中集成电路的加固技术，旨在通过电路设计提高集成电路的可靠性与耐用性，同时最大化降低成本开销，包括芯片“硬成本”以及开发周期“时间成本”。

教育背景：

复旦大学，微电子学与固体电子学，博士 （导师：曾晓洋教授）

卡尔斯鲁厄理工学院（德国），电子工程，联合培养博士 （导师：Prof. Mehdi Tahoori）

工作学术经历：

2024年09月 - 至今 复旦大学微电子学院，青年研究员

2022年02月 - 2024年08月 复旦大学微电子学院，博士后/助理研究员

人才称号：

上海市浦江人才 2022

学术兼职：

CCF容错计算专委会执行委员

代表性成果：

[1] Yan Li, Chao Chen, Xu Cheng, Jun Han, and Xiaoyang Zeng, “DMBF: Design Metrics Balancing Framework for Soft-Error-Tolerant Digital Circuits Through Bayesian Optimization,” IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 4015–4027, 2023, doi: 10.1109/TCSI.2023.3302341.

[2] Yan Liu, Yan Li, Xu Cheng, Jun Han, and Xiaoyang Zeng, “A Non-Redundant Latch With Key-Node-Upset Obstacle of Beneficial Efficiency for Harsh Environments Applications,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 4, pp. 1639–1648, Apr. 2023, doi: 10.1109/TCSI.2023.3237706.

[3] Chenyu Zhang, Yan Li, Xu Cheng, Jun Han, and Xiaoyang Zeng. “Impact of Tap Cell on Single Event Transient in 28-nm CMOS Technology.” 2022 European Conference on Radiation and its Effects on Components and Systems (RADECS), 2022.

[4] Chiyu Tan, Yan Li, Xu Cheng, Jun Han, and Xiaoyang Zeng. “Pulse Quenching Effect Characterized by Inverter Chains under Heavy-ion Irradiation in 28-nm CMOS Technology.” 2022 European Conference on Radiation and its Effects on Components and Systems (RADECS), 2022.

[5] Chiyu Tan, Yan Li, Xu Cheng, Jun Han, and Xiaoyang Zeng, “General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework,” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 68, no. 7, pp. 3044–3057, Jul. 2021.

[6] Yan Li, Jun Han, Xiaoyang Zeng, and Mehdi B. Tahoori, “TRIGON: A Single-phase-clocking Low Power Hardened Flip-Flop with Tolerance to Double-Node-Upset for Harsh Environments Applications,” in 2021 Design, Automation Test in Europe Conference Exhibition (DATE), Feb. 2021.

[7] Yan Li, Xiaoyoung Zeng, Zhengqi Gao, Liyu Lin, Jun Tao, Jun Han, Xu Cheng, Mehdi B. Tahoori, and Xiaoyang Zeng. “Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit,” in 2020 57th ACM/IEEE Design Automation Conference (DAC), Jul. 2020.

[8] Yan Li, Xu Cheng, Chiyu Tan, Jun Han, Yuanfu Zhao, Liang Wang, Tongde Li, Mehdi B.  Tahoori, and Xiaoyang Zeng, “A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application,” IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 67, no. 9, pp. 1619–1623, Sep. 2020.

[9] Yan Li, Jun Han, XiaoyoungZeng, and Xiaoyang Zeng. “A Multi-Objective Optimization Framework to Design Soft-Error-Immune Circuit.” 2019 European Conference on Radiation and its Effects on Components and Systems(RADECS), 2019.