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研究方向：
模数转换器设计，混合信号/射频/模拟集成电路设计
教育背景：
2012年 - 2018年 加州大学洛杉矶分校，电子与计算机工程，博士
2010年 - 2012年 加州大学洛杉矶分校，电子工程，硕士
2006年 - 2010年 复旦大学，微电子学，学士
工作学术经历：
2021年 - 至今 复旦大学. ，青年研究员
2019年 - 2021年 苹果 Apple Inc. ，射频集成电路工程师
2017年 - 2019年 博通 Broadcom Inc. ，硬件研发工程师
获奖或荣誉：
2014-2015 Broadcom Foundation Fellowship
2013-2014 Analog Devices Outstanding Student Designer Award
代表性成果：
n Y. Tian, J. Gu, W. He, S. Liu, H. Xu* and N. Yan*, “An 8-to-28GHz 8-Phase Clock Generator Using Dual-Feedback Ring Oscillator in 28nm CMOS,”IEEE ISSCC, 2025.
n Y. Mao, H. Gao, J. Shao, X. Lin, P. Wu, P. Lu, H. Xu* and N. Yan*, “An All-digital Spread-Spectrum Clock Generator with Feedforward Gain Calibration for LPWAN Chirp Transmission System,” IEEE TCAS-II, 2025.
n H. Qin, J. Gu, H. Xu*, Z. Xu, P. Jia and N. Yan*, “A 25–31-GHz Compact True Power Detector With >33-dB Dynamic Range and Intrinsic Phase Offset Compensation in 40-nm Bulk CMOS,” IEEE JSSC, 2025.
n J. Bi, H. Xu*, T. Zou, Y. Zeng, Y. Tian, W. He, G. Gu, Z. Jiao, S. Liu, Z. Zhu and N. Yan*, “A 5–18-GHz Reconfigurable Quadrature Receiver with Enhanced I–Q Isolation and 100–500-MHz Baseband Bandwidth,” IEEE JSSC, 2025.
n T. Iizuka*, R. Takenaka, H. Xu and A. Abidi, “Systematic Equation-Based Design of a 10-Bit, 500-MS/s Single-Channel SAR A/D Converter With 2-GHz Resolution Bandwidth,” IEEE OJ-SSCS, 2024.
n H. Qin, J. Gu, H. Xu*, Z. Xu, P. Jia and N. Yan*, “A 25-31GHz Compact True Power Detector with >33dB Dynamic Range in 40nm Bulk CMOS,” IEEE RFIC, 2024.
n A. Sun, H. Qin, H. Xu* and N. Yan*, “A Compact 0.1-19.7GHz Ultra-Wideband Power Amplifier with ±0.5dB Gain Ripple in 28 nm CMOS Process,” IEEE ESSERC, 2024.
n R. Chen, A. Lee, Y. Hu, H. Xu* and X. Kou*, “A 12-bit 75 MS/s Asynchronous SAR ADC with Gain-Boosting Dynamic Comparator,” IEEE ISCAS, 2025.
n Y. Wang, H. Xu, G. Li, S. Liu, Y. Liu, R. Yin, H. Pan and N. Yan*, “An 8-14GHz 180fs-rms DTC-Less Fractional ADPLL with ADC-Based Direct Phase Digitization in 40nm CMOS,” IEEE CICC, 2024.
n H. Xu, S. Ji, Y. Wang, X. Lin, H. Min and N. Yan*, “Analysis and Design of a Sub-Sampling PLL of Low Phase Noise and Low Reference Spur,” IEEE TCAS-I, 2024.
n H. Xu, J. Bi, T. Zou, W. He, Y. Zeng, J. Gu, Z. Jiao, S. Liu, Z. Zhu and N. Yan*, “A 5-to-16GHz Reconfigurable Quadrature Receiver with 50% Duty-Cycle LO and IQ-Leakage Suppression,” IEEE ISSCC, 2024.
n H. Qin, J. Gu, H. Xu*, W. Liu, K. Han, R. Yin, Z. Duan, H. Gao and N. Yan, “A 26-30GHz Digitally-Controlled Variable Gain Power Amplifier with Phase Compensation and Third Order Nonlinearity Cancellation Technique,” IEEE A-SSCC, 2023.
n Y. Liu, H. Gao, H. Xu*, P. Lu and N. Yan*, “A 10-bit 563-fs Step Constant-Slope Digital-to-Time Converter in 40-nm CMOS With Nonlinearity Cancellation and Range Extension Techniques,” IEEE TCAS-I, 2024.
n Y. Wang, J. Shi, H. Xu*, S. Ji, Y. Mao, T. Zou, J. Tao, H. Min and N. Yan*, “Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9–14.3-GHz 85-fs-rms Jitter PLL,” IEEE JSSC, 2023.
n T. Zou, H. Xu*, Y. Wang, W. Liu, T. Han, M. Tian, W. Zhu and N. Yan*, “A 6–12 GHz Wideband Low-Noise Amplifier With 0.8–1.5 dB NF and ±0.75 dB Ripple Enabled by the Capacitor Assisting Triple-Winding Transformer,” IEEE TCAS-I, 2023.
n J. Gu, H. Qin, H. Xu*, W. Liu, K. Han, R. Yin, L. Deng, X. Shen, Z. Duan, H. Gao and N. Yan*, “A 23-30 GHz 4-Path Series-Parallel-Combined Class-AB Power Amplifier with 23 dBm Psat, 38.5% Peak PAE and 1.3° AM-PM Distortion in 40nm Bulk CMOS,” IEEE RFIC, 2023.
n A. Sun, J. Gu, H. Xu*, W. Liu, K. Han, R. Yin, Z. Duan, H. Gao and N. Yan*, “A 26-32GHz Differential Attenuator with 0.23dB RMS Attenuation Error and 11.2dBm IP1dB in 40nm CMOS Process,” IEEE IMS, 2023.
n Y. Tian, J. Gu, H. Xu*, W. Liu, Z. Duan, H. Gao, N. Yan*, “A 26-32GHz 6-bit Bidirectional Passive Phase Shifter with 14dBm IP1dB and 2.6° RMS Phase Error for Phased Array System in 40nm CMOS,” IEEE IMS, 2023.
n T. Zou, H. Xu*, Y. Wang, W. Liu, T. Han, Z. Wang, N. Li, M. Tian, W. Zhu and N. Yan*, “A Capacitor Assisting Triple-Winding Transformer Low-Noise Amplifier with 0.8-1.5dB NF 6-12GHz BW ±0.75dB Ripple in 130nm SOI CMOS,” IEEE RFIC, 2022.
n T. Iizuka, H. Xu and A. Abidi, “A Tutorial on Systematic Design of CMOS A/D Converters: Illustrated by a 10b, 500MS/s SAR ADC with 2GHz RBW,” IEEE ESSCIRC, 2021.
n H. Xu* and A. Abidi, “Analysis and Design of Regenerative Comparators for Low Offset and Noise,” IEEE TCAS-I, 2019.
n D. Yang, H. Darabi, A. Abidi, H. Xu, H. Wu and Z. Wang, “A Calibration-Free Triple-Loop Bang-Bang PLL Achieving 131fsrms Jitter and -70dBc Fractional Spurs,” IEEE ISSCC, 2019.
n H. Xu* and A. Abidi, “Design Methodology for Phase-Locked Loops using Binary (Bang-Bang) Phase Detectors,” IEEE TCAS-I, 2017.
n D. Murphy*, H. Darabi and H. Xu, “A Noise-Cancelling Receiver Resilient to Large Harmonic Blockers,” IEEE JSSC, 2015.
n A. Abidi and H. Xu, “Understanding the Regenerative Comparator Circuit,” IEEE CICC, 2014.
n D. Murphy, H. Darabi and H. Xu, “A Noise-Cancelling Receiver with Enhanced Resilience to Harmonic Blockers,” IEEE ISSCC, 2014.
