招生需求：

欢迎有志于模拟/射频及数模混合集成电路研究与设计、勇于创新的硕士、博士研究生及博士后加入。

实验室提供开放的科研环境，与工业界接轨的项目和实习机会。

研究方向：

高性能模拟、射频及数模混合集成电路设计

 1.高性能振荡器、锁相环、频率综合器和时钟电路设计

 2.高速数据接口电路、有线通信、光电收发机设计

 3.高性能低功耗无线射频收发机设计

课程教学：

 1.先进模拟集成电路设计

 2.专业英语

 3.微电子前沿讲座、高中生先修课堂

教育背景：

2008年09月-2013年03月美国俄勒冈州立大学，电子与计算机工程，博士

2005年09月-2008年06月复旦大学，微电子学，硕士

2001年09月-2005年07月复旦大学，微电子学，学士

工作经历：

2020年11月 - 至今复旦大学，研究员，博士生导师
2013年04月 - 2020年10月三星半导体（美国），高级工程师、主任工程师、高级主任工程师

获奖或荣誉：

 1.2017 Samsung President’s Incentive Award

 2.2012 Analog Devices OSU Graduate Fellowship

1. 1. Y. Liu, Y. Li, K. Wang, X. Yu, and R. Ni, A 21.6fs_rms-jitter, -260.7dB-FoM Fractional-N PLL Enabled by an Intrinsically Linear Variable-Slope SPD for Quantization Error Cancellation, IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2026.

2. 2. Y. Li, Y. Liu, K. Wang, D. Pu, X. Yu, and R. Ni, A 10.2-to-16.2GHz Dual-Mode-Transformer-Based Wideband Series-Resonance VCO Achieving >201.1dBc/Hz FoM_T at a 10MHz Offset, IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2026.

3. 3. Y. Li, D. Pu, X. Yu and R. Ni, A Quad-Core Series-Resonance VCO Enabled by Circular Lsecondary and Stacked Lprimary Achieving 198.9-dBc/Hz FoM at 10MHz, IEEE International Symposium on Circuits and Systems (ISCAS), Shanghai, China, 2026.

4. 4. Y. Li, C. Gao, X. Cai, X. Yu and R. Ni, A 0.1-V Transformer-Based Class-D VCO Achieving 0.9-V Output Swing and >193.8-dBc/Hz FoM at 10-MHz Offset, IEEE International Symposium on Circuits and Systems (ISCAS), Shanghai, China, 2026.

5. 5. W. Chen, J. Chen, M. Li, Y. Liu, Y. Wu, P. Zhou, P. Y. Chiang, and R. Ni,  A 4x112 Gb/s PAM4 Current-Reuse VCSEL Driver with a High-Bandwidth VGA in 130 nm BiCMOS, IEEE International Symposium on Circuits and Systems (ISCAS), Shanghai, China, 2026.

6. 6. Y. Liu, K. Wang, Y. Li, Y. Liu, X. Yu and R. Ni, A 37.5fs-rms Jitter and −254.1dB FoM Fractional-N Sampling PLL with Reference-Phase-Selection and Complementary-DTC Achieving 8× DTC Range Reduction and Zero DTC Delay Offset, IEEE Custom Integrated Circuits Conference (CICC), Boston, MA, USA, 2025.

7. 7. X. Xiu, T. Huang, Q. Li, M. Liu, H. Min, X. Yu and R. Ni, An Ultra-Low Power 915 MHz LO with Adaptive Frequency Calibration for IoT Wake-Up Receivers, IEEE International Symposium on Circuits and Systems (ISCAS), London, United Kingdom, 2025.

8. 8. J. Lee, S. Han, J. Lee, B. Kang, J. Bae, J. Jang, S. Oh, S. Ahn, S. Kang, Q. Bui, K. Son, H. Lim, D. Jeong, R. Ni, Y. Zuo, I. Jong, C. Yao, S. Heo, T. Cho, and I. Kang, A Sub-6GHz 5G New Radio RF Transceiver Supporting EN-DC with 3.15Gb/s DL and 1.27Gb/s UL in 14nm FinFET CMOS, IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2019.

9. 9. W. Wu, C. Yao, K. Godbole, R. Ni, P. Chiang, Y. Han, Y. Zuo, A. Verma, I. Lu, S. Son, and T. Cho, A 5.5-7.3 GHz Analog Fractional-N Sampling PLL in 28-nm CMOS with 75 fsrms Jitter and −249.7 dB FoM, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Philadelphia, PA, USA, 2018.

10. 10. S. Ko, C. Yao, J. Lee, S. Han, D. Kwon, W. Loke, R.Ni, and T. Cho, Digital PLL design challenges for cellular RFICs, IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Seoul, Korea (South), 2017.

11. 11. C. Yao, W. Loke, R. Ni, Y. Han, H. Li, K. Godbole, Y. Zuo, S. Ko, N. Kim, S. Han, I. Jo, J. Lee, J. Han, D. Kwon, C. Kim, S. Kim, S. Son, and T. Cho, 24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and −78dBc fractional spur for cellular RFICs, IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2017.

12. 12. R. Ni, K. Mayaram, and T. Fiez, A 915MHz, 6Mb/s, 80pJ/b BFSK receiver with −76dBm sensitivity for high data rate wireless sensor networks, Symposium on VLSI Circuits (VLSI), Honolulu, HI, USA, 2014.

13. 13. R. Ni, K. Mayaram, and T. Fiez,  A 2.4GHz hybrid PPF based BFSK receiver with ±180ppm frequency offset tolerance for wireless sensor networks, Symposium on VLSI Circuits (VLSI), Honolulu, HI, USA, 2012.

1. 1. C. Gao, J. Chen, L. Sun, Z. Jin, X. Yu and R. Ni, A 0.66-pJ/b 42-Gb/s NRZ Receiver for Short-Reach Wireline Communications in 28-nm CMOS, in IEEE Microwave and Wireless Technology Letters (MWTL), Jan. 2026.

2. 2. L. Sun, Y. Liu, Z. Jin, X. Yu and R. Ni, A 50-Gb/s 0.76 pJ/b NRZ Transmitter With MUX-FFE Combination and Linear Driver in 28-Nm CMOS, in IEEE Access, vol. 14, pp. 5268-5276, Jan. 2026.

3. 3. Y. Li, X. Yu and R. Ni, An 11.5 GHz 203.7 dBc/Hz FoMA Multi-Tap Inductor Based Single-Core Fixed-Supply Reconfigurable VCO Achieving 8.2dB PN Scaling, inIEEE Transactions on Circuits and Systems II: Express Briefs(TCAS-II), Dec. 2025.

4. 4. L. Sun, Z. Jin, Y. Liu, X. Yu, and R Ni, A 50 Gb/s 0.42 pJ/b Non-Return-to-Zero Transmitter for Extra-Short-Reach SerDes in Electronics, vol. 14, no. 10, pp. 1955-1966, May 2025.

5. 5. J. Lee, S. Han, J. Lee, B. Kang, J. Bae, J. Jang, S. Oh, J. Chang, S. Kang, K. Son, H. Lim, D. Jeong, I. Jong, S. Baek, J. Lee, R. Ni, Y. Zuo, C. Yao, S. Heo, T. Cho, and I. Kang, A Sub-6-GHz 5G New Radio RF Transceiver Supporting EN-DC With 3.15-Gb/s DL and 1.27-Gb/s UL in 14-nm FinFET CMOS, in IEEE Journal of Solid-State Circuits (JSSC), vol. 54, no. 12, pp. 3541-3552, Dec. 2019.

6. 6. W. Wu, C.W. Yao, K. Godbole, R. Ni, P. Chiang, Y. Han, Y. Zuo, A. Verma, I. Lu, S. Son, and T. Cho, A 28-nm 75-fsrms Analog Fractional- N Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction, in IEEE Journal of Solid-State Circuits (JSSC), vol. 54, no. 5, pp. 1254-1265, May 2019.

7. 7. C. Yao, R. Ni, C. Lau, W. Wu, K. Godbole, Y. Zuo, S. Ko, N. Kim, S. Han, I. Jo, J. Lee, J. Han, D. Kwon, C. Kim, S. Kim, S. Son, and T. Cho, A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration, in IEEE Journal of Solid-State Circuits (JSSC), vol. 52, no. 12, pp. 3446-3457, Dec. 2017.

8. 8. R. Ni, K. Mayaram, and T. Fiez, A 2.4 GHz Hybrid Polyphase Filter Based BFSK Receiver With High Frequency Offset Tolerance for Wireless Sensor Networks, in IEEE Journal of Solid-State Circuits (JSSC), vol. 48, no. 5, pp. 1250-1263, May 2013.