本人的研究组以人机融合智能系统与芯片为科研目标，同时面向5G边缘计算的智能、安全应用开展RISC-V等开源芯片技术的产学研合作。
人类与机器之间的交互关系已成为一个重要的科学问题，人们必须探索通过更加合理的人机关系来增强人机作为协同系统完成指定任务、改造环境的能力。芯片已成为人类最重要的工具之一，如何让芯片具有智能，如何让芯片在人机融合智能系统中发挥关键性作用是当前亟待研究的前沿性课题。
开源芯片是未来芯片设计行业的重要趋势，它将带来芯片设计方法学和芯片产业生态链的革命性变化，从而有效支持人工智能、物联网、5G等新一代信息技术和数字经济发展。产教融合的开源实践项目将成为培养集成电路设计人才的重要途径。
欢迎有志于探索科学问题、从事技术创新和锻炼工程实践能力的同学加入！招收有微电子、电路与系统、计算机科学、智能科学等相关背景的硕士生、博士生、科研助理、博士后。
了解智能体系架构与开源芯片的相关工作，欢迎访问本研究组的知乎专栏（IA&C Lab@Fudan）：https://zhuanlan.zhihu.com/c_1236963527866175488
近期正在承担的主要科研项目：
1.作为首席专家承担了国家重点研发计划“光电子与微电子器件及集成”重点专项“高能效人机交互芯片技术”项目
2.作为项目负责人承担了国家自然科学基金重点项目“自感知自组织异构众核智能芯片的互连与存储技术研究”
3.作为项目负责人承担了国家自然科学基金面上项目“机器学习芯片系统的弹性能效技术研究”
4.与西安交通大学、中科院微电子所共同承担了国家自然科学基金人工智能基础研究应急管理项目“高效深度神经网络处理的架构、电路与器件协同设计技术研究”
5.围绕RISC-V处理器和人工智能加速器等开源芯片技术的产学研合作项目
研究方向：
1.人机融合智能系统：1）人机融合智能系统的建模和测评技术；2）基于人体行为和语音识别的人机交互智能算法与芯片；3）基于生物医电信号的人机交互智能算法与芯片。
2.体系架构设计方法学：1）自感知自组织智能芯片架构探索与ESL（Electronic System Level）设计方法；2）DSA（Domain Specific Architecture）体系架构设计；3）人工智能专用架构的编译器定制优化技术（AI Compiler）。
3.开源芯片技术：1）基于RISC-V指令架构的处理器扩展设计技术与SoC系统定制集成方法；2）面向边缘计算人工智能的数据并行处理器开源芯片设计；3）面向5G安全和高性能区块链计算的有限域代数处理器开源芯片设计。
教育背景：
复旦大学，微电子学与固体电子学专业，理学博士学位
学术经历：
2016年12月-至今复旦大学微电子学院，研究员
2012年12月-2016年11月复旦大学微电子学院，副研究员
2006年07月-2012年11月复旦大学信息科学与工程学院，助理研究员
2010年曾赴欧洲国际微电子中心（IMEC）和比利时鲁汶大学进修访问
学术兼职：
中国计算机学会计算机工程与工艺专委会常务委员
微电子领域知名学术期刊Microelectronics Journal编委会委员
近期以第一作者和通信作者发表的主要期刊论文（part）:
[1]Jun Yin, Jun Han, Ruiqi Xie, Chenghao Wang, Xuyang Duan, Yitong Rong, Xiaoyang Zeng, Jun Tao, MC-LSTM: Real-time 3D Human Action Detection System for Intelligent Healthcare Applications, IEEE Transactions on Biomedical Circuits and Systems ( Early Access ), March 2021
[2]Guozhu Xin, Jun Han, Tianyu Yin, Yuchao Zhou, Jianwei Yang, Xu Cheng, Xiaoyang Zeng, VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 8, pp. 2672-2684, Aug. 2020
[3]Bingyi Zhang, Jun Han, Zhize Huang, Jianwei Yang, Xiaoyang Zeng, “A Real-time and Hardware-efficient Processor for Skeleton-based Action Recognition with Lightweight Convolutional Neural Network”, IEEE Transactions on Circuits and Systems II: Express Briefs, 66(12), pp. 2052-2056, Dec. 2019.
[4]Jun Han, Yicheng Zhang, Shan Huang, Mengyuan Chen, Xiaoyang Zeng, “An Area-Efficient Error-Resilient Ultra-Low-Power Subthreshold ECG Processor”, IEEE Transactions on Circuits and Systems II: Express Briefs 63(10), pp 984-988, 2016/10
[5]Jun Han, Renfeng Dou, Lingyun Zeng, Shuai Wang, Zhiyi Yu, Xiaoyang Zeng, A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation, IEEE Transactions on Circuits and Systems I: Regular Papers, 62(5), pp 1372-1381, 2015/5
[6]Jun Han, Yang Li, Zhiyi Yu, Xiaoyang Zeng, A 65 nm Cryptographic Processor for High Speed Pairing Computation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(4), pp 692-701, 2015/4
[7]Jun Han, Shuai Wang, Wei Huang, Zhiyi Yu, Xiaoyang Zeng, “Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(12), pp 2325-2330, 2013/12
[8]Yao Zou, Jun Han, Sizhong Xuan, Shan Huang, Xinqian Weng, Dabin Fang, Xiaoyang Zeng, An Energy-Efficient Design for ECG Recording and R-Peak Detection Based on Wavelet Transform, IEEE Transactions on Circuits and Systems II: Express Briefs, , 62(2), pp 119-123, 2015/2
[9]Gaowei Xu, Jun Han, Yao Zou, Xiaoyang Zeng, A 1.5-D Multi-Channel EEG Compression Algorithm Based on NLSPIHT, IEEE Signal Processing Letters, 22(8), pp 1118-1122, 2015/8
[10]Renfeng Dou, Jun Han, Yifan Bo, Zhiyi Yu, Xiaoyang Zeng, “An Efficient Implementation of Montgomery Multiplication on Multicore Platform With Optimized Algorithm, Task Partitioning, and Network Architecture”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(11), pp 2245-2255, 2014/11
[11]Zou Yao, Han Jun, Weng Xinqian, Zeng Xiaoyang, “An Ultra-Low Power QRS Complex Detection Algorithm Based on Down-Sampling Wavelet Transform”, IEEE Signal Processing Letters, 20(5), pp 515-518, 2013/5
[12]Jianwei Yang, Fan Dai, Jielin Wang, Jianmin Zeng, Zhang Zhang, Jun Han, Xiaoyang Zeng, “Countering power analysis attacks by exploiting characteristics of multicore processors”, IEICE Electronics Express, Volume 15 (2018) Issue 7
[13]Zhang Yuli, Han Jun, Weng Xinqian, He Zhongzhu, Zeng Xiaoyang, “Design approach and implementation of application specific instruction set processor for SHA-3 blake algorithm”, IEICE Transactions on Electronics, v E95-C, n 8,pp 1415-1426, August 2012
[14]Zhou Weina, Dai Lin, Zou Yao, Zeng Xiaoyang, Han Jun, “A high speed reconfigurable face detection architecture based on adaboost cascade algorithm”, IEICE Transactions on Information and Systems, v E95-D, n 2, pp 383-391,February 2012
近期以第一作者和通信作者发表的主要会议论文（part）:
[1]Guozhu Xin, Yifan Zhao, Jun Han, A Multi-Layer Parallel Hardware Architecture for Homomorphic Computation in Machine Learning, Circuits and Systems (ISCAS) 2021 IEEE International Symposium on, pp. 1-5, 2021.
[2]Jun Yin, Jun Han, Chenghao Wang, Bingyi Zhang, Xiaoyang Zeng, “A Skeleton-based Action Recognition System for Medical Condition Detection”, IEEE Biomedical Circuits and Systems Conference (BioCAS), 2019, 2019/10/17-2019/10/19, Nara, Japan
[3]Yalong Pang, Jun Han, Jianmin Zeng, Yujie Huang, Xiaoyang Zeng, Instruction set extension and hardware acceleration for SVM application toward a vector processor, 2017 International SoC Design Conference (ISOCC), 2017/11/5-2017/11/8, Seoul, Korea
[4]Shan Huang, Jun Han, Xin Li, Zongxian Yang and Xiaoyang Zeng, “A Low-Cost and Energy-Efficient EEG Processor for Continuous Seizure Detection Using Wavelet Transform and AdaBoost”, IEEE Biomedical Circuits and Systems Conference (BioCAS) 2016, 2016/10/17-2016/10/19, Shanghai, China
[5]Weizhen Wang, Jun Han, Zhicheng Xie, Shan Huang and Xiaoyang Zeng, “Cryptographic Coprocessor Design for IoT Sensor Nodes”, 13th International SoC Design Conference (ISOCC), 2016, 2016/10/23-2016/10/26, Jeju, Korea
[6]Mengyuan Chen, Jun Han, Yicheng Zhang, Yao Zou, Yi Li and Xiaoyang Zeng, An error-resilient wavelet-based ECG processor under voltage overscaling, IEEE Biomedical Circuits and Systems Conference (BioCAS), 2014, 2014/10/22-2014/10/24, Lausanne, Switzerland
[7]Shuang Wang, Jun Han, Yang Li, Yifan Bo, Xiaoyang Zeng, “A 920MHz quad-core cryptography processor accelerating parallel task processing of public-key algorithms”, IEEE Custom Integrated Circuits Conference (CICC), 2013, 2013/9/22-2013/9/25, San Jose, CA, USA
[8]Yang Li, Jun Han, Shuai Wang, Dabin Fang and Xiaoyang Zeng, “An 800Mhz Cryptographic Pairing Processor in 65nm CMOS”, IEEE Asian Solid-State Circuits Conference (A-SSCC), 2012, November 12-14, 2012, Kobe, Japan
