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来金梅

研究员博士生导师

电话51355237

邮箱jmlai@fudan.edu.cn

地址复旦大学张江校区微电子楼229室

研究所处理器与系统芯片设计研究所

主要经历(教育及工作经历):

1995年02月-1998年02月:上海交通大学电院 博士研究生
1998年02月-2000年06月:浙江大学信电系 博士后
2000年06月-2003年06月:复旦大学专用集成电路与系统国家重点实验室 博士后
2007年06月:比利时微电子研究中心IMEC培训学习
2003年06月-至今:复旦大学微电子学院 教授

 

研究方向:

 1.可编程系统芯片架构及电路设计方法

 2.可编程系统芯片EDA软件算法研究

 3.SoC FPGA系统芯片功能及电参数自动化高效测试方法

 4.SoC FPGA智能一体化通用测试验证调试平台设计

 5.基于SoC FPGA的深度学习研发平台设计

 6.嵌入式可编程 IP 核及其EDA软件算法

 7.可重构、可进化FPGA电路研究

 

主讲课程

  1. “信号与通信系统 ” (本科生)

  2. “集成电路设计基础”( 科硕研究生)

  3. “VLSI系统设计导论”(工硕研究生)

  4. “集成电路设计透视” (书院课程)


荣誉和奖励:

  1. 上海市巾帼创新奖,2007

  2. 适用于数据通路应用的可编程逻辑器件及其软件系,获高等学校科技进步二等奖(2),颁证(奖)单位:中华人民共和国教育部,2007

  3. 年度微电子研究院先进个人奖,2007

  4. 年度学院奖教金二等奖,2008

 

 

近期发表论文:

 1.Zhengjie Li, Yuanlong Xiao, Yufan Zhang, Yunbing Pang,Jian Wang, Jinmei Lai Transistor-Level Optimization Methodology fot GRM FPGA Interconnect Circuits, FPGA2019,February 24-26, Seaside, CA, USA

 2.Zhengjie Li, Yuanlong Xiao, Yufan Zhang, Yunbing Pang, Chengyu Hu, Jian Wang, Jinmei Lai,An Automatic Transistor-Level Tool for GRM FPGA Interconnect Circuits Optimization, GLSVLSI ’19, May 9–11, 2019, Tysons Corner, VA, USA

 3.Chengyu Hu, Qinghua Duan, Liran Hu, Peng Lu,Zhengjie Li, Meng Yang, Jian Wang, and Jinmei Lai,An Analytical-based Hybrid Algorithm for FPGA Placement,GLSVLSI ’19, May 9–11, 2019, Tysons Corner, VA, USA

 4.Chengyu Hu, Peng Lu, Meng Yang, JianWang and Jinmei Lai,A SA-based parallel method for FPGA placement,IEICE Electronics Express, 2018,Vol.15, No.24, 1–8

 5.Yunbing Pang, Jiqing Xu, Yufan Zhang, Xinxuan Tao*, Jian Wang, Meng Yang, Jinmei Lai*,Research on Circuit-Level Design of High Performance and Low Power FPGA Interconnect Circuits in 28nm Process,ICSICT 2018,2018 IEEE 14th International Conference on Solid-State and Integrated Circuit Technology, Oct.31-Nov. 3,2018,Qingdao,China

 6.Yufan Zhang, Yunbing Pang, Jiqing Xu, Xinxuan Tao*, Jian Wang, Meng Yang, Jinmei Lai*, Research on Design and Test Method of High Performance 6 Input LUT,ICSICT 2018,2018 IEEE 14th International Conference on Solid-State and Integrated Circuit Technology, Oct.31-Nov. 3,2018,Qingdao,China

 7.Zhen Yang, Chuanzeng Liang, Jian Wang, and Jinmei Lai ,Testing Modern FPGA Local Interconnects Based On Repeatable Configuration Modules, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2016)

 8.Yuanlong Xiao, Jian Wang, and Jinmei Lai,A Universal Automatic On-Chip Measurement of FPGA's Internal Setup and Hold Times,IEICE Electronics Express, Publicized December 10, 2016

 9.Xu Hanyang,Lai Jinmei,A FPGA Prototype Design Emphasis on Low Power Technique,FPGA2014, Proceedings of the 2014 ACM/SIGDA International Symposium on Field Programmable Gate Array, Monterey California,USA

 10.Chun Zhu, Jian Wang, Jinmei Lai,A Novel Net-Partition-Based Multithread FPGA Routing Method,23rd international conference on field programmable logic and applications, FPL 2013 , Porto,Portugal,Sept.2-4,2013,oral

 11.Hanyang Xu, Jian Wang, and Jinmei Lai,Prototyping design of a flexible DSP block with pipeline structure for FPGA,IEICE Electronics Express,Publicized August 19, 2016

 12.Lei Li, Jinmei Lai,Design and implementation of clock network for nanometer FPGA,IEICE Electronics Express,Vol.12,No.5,1-10,2015

 13.Xu Hanyang, Wang Jian,Jinmei Lai,,A FPGA Prototype Design Emphasis on Low Power Technique,ACM/SIGDA International Symposium on Field-Programmable Gate Arrays ,FPGA 2014

 14.Zhen Yang, Chuanzeng Liang, Jian Wang, and Jinmei Lai, A new automatic method for testing interconnect resources in FPGAs based on general routing matrix,IEICE Electronics Express,Vol. 12 (2015) No. 20 ,1-11, 2015

 15.Chun Zhu, Jian Wang, Jinmei Lai,A Novel Net-Partition-Based Multithread FPGA Routing Method,23rd international conference on field programmable logic and applications, FPL 2013 , Porto,Portugal,Sept.2-4,2013

 16.FU Yong,WANG Chi ,CHEN Liguang, LAI Jinmei,A Full Coverage Test Method for Configurable Logic Blocks in FPGA,电子学报:英文版,2013年第3期

 17.Wang, Zhen, Xie, Ding, Lai, Jinmei,FPGA interconnect architecture exploration based on a statistical model,21st International Conference on Field Programmable Logic and Applications, FPL 2011, pp 447-452, 2011/9/5

 18.Duan, Xueyan, Wang, Liyun, Lai, Jinme,Effect of charge sharing on the single event transient response of CMOS logic gates,Journal of Semiconductors, 32(9), pp 095008-1-095008-6, 2011

 19.Xie, D; Lai, JM; Tong, JR, Research of Efficient Utilization Routing Algorithm for Current FPGA, CHINESE JOURNAL OF ELECTRONICS, 2010, 19(1) 

 20.Yuanlong Xiao1, Jian Wang, Jinmei Lai,,A Power Efficient Current-Mode Differential Driver for FPGAs,The 11th International Conference on ASIC (ASICON 2015),Wangjiang Hotel, Chengdu, China, November 3-6, 2015.

 21.Fang Sun, Jin-meiLai, Iterative optimization algorithmfor sound localization, The 11th International Conference on ASIC (ASICON 2015),Wangjiang Hotel, Chengdu, China, November 3-6, 2015.

 22.Yuanpei Gao, Haijiang Ye, Jian Wang1, Jinmei Lai1,FPGA Bitstream Compression and Decompression based on lz77 Algorithm and BMC Technique, The 11th International Conference on ASIC (ASICON 2015),Wangjiang Hotel, Chengdu, China, November 3-6, 2015.

 23.李华冈,来金梅、王健等,带时序约束的FPGA时序驱动布局方法,中国发明专利,专利号,ZL2012102489032,授权公告日:2015.01.07

 24.来金梅、王健等,自动化测试中扩展输入输出通道的方法,中国发明专利,专利号,ZL2012104771470,授权公告日:2015.05.13

 25.付勇,来金梅、王健等,基于查找表结构的FPGA可编程逻辑单元的遍历测试,ZL2010101865000,授权公告日:2015.11.25

 26.张昕睿,王健,来金梅等,FPGA中具有多种写入模式的BlockRAM,中国发明专利,专利号,ZL2013101140531,授权公告日:2015.12.02

 27.来金梅,方浩帅,王健,发明专利:FPGA时序约束布局方法, 申请号:2015102890750,申请公布日:20150601

 28.发明专利:来金梅,杨震,王健,基于FPGA硬件结构的时钟网络遍历测试方法, 申请号:2015100172869,申请公布日:20150