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FPGA Technology Mapping for LUTs, LUT Structures, and Programmable Cells

发布日期:2019-11-15 浏览量:

题   目:FPGA Technology Mapping for LUTs, LUT Structures, and Programmable Cells

报告人:Dr. Alan Mishchenko (UC Berkeley)

时   间:2019年11月21日下午1:00 - 3:00

地   点:张江校区微电子楼369室


Abstract

A structural technology mapper is a computation engine used in EDA tools. The mapper takes a simple circuit structure, such as an and-inverter graph, and a technology library. The mapper produces a structural cover of the circuit in terms of the library primitives while optimizing cost functions, such as area, delay, power, etc. 

This talk describes the design of an efficient cut-based technology mapper and its applications in the design flow for FPGAs as well as in logic synthesis (to minimize circuit structures) and Boolean satisfiability (to minimize conjunctive normal forms given to the solver). When it comes to FPGA mapping, we will discuss three types of primitives: 

(1) k-input lookup tables (LUTs), which can implement any k-input logic function

(2) n-input structures composed of several k-LUTs

(3) n-input single-output programmable cells composed of several k-LUTs and other cells such as MUXes and AND/OR gates, where k is typically 4 or 6, while n can be up to 16. 


Biography

Alan graduated with M.S. from Moscow Institute of Physics and Technology (Moscow, Russia) in 1993 and received his Ph.D. from Glushkov Institute of Cybernetics (Kiev, Ukraine) in 1997. In 2002, Alan joined the EECS Department at University of California, Berkeley, where he is currently a full researcher. His research is in computationally efficient logic synthesis and formal verification.


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