讲座信息:Software-Hardware Co-Design for Efficient Neural Network Acceleration on FPGA

汪玉(清华大学)

时 间:2017年7月9日(周日)9:30
地 点:张江校区微电子楼369会议室

Abstract
Artificial neural networks, which dominate artificial intelligence applications such as object recognition and speech recognition, are rapidly evolving. For wide applicability of neural networks, customized hardware is necessary. FPGA can be an ideal platform for accelerating inferencing in neural network since it is programmable and can achieve much higher energy efficiency compared with general-purpose processors. We propose a complete design flow to achieve both fast deployment and high energy efficiency for accelerating neural networks on FPGA [FPGA’16, FPGA’17 best paper]. Deep compression and data quantization are employed to exploit the redundancy in algorithm and reduce both computational and memory complexity. Two architecture designs for CNN and DNN/RNN are proposed together with compilation environment. Evaluated on Xilinx Zynq 7000 and Kintex Ultrascale series FPGA with real-world neural networks, up to 15 times higher energy efficiency can be achieved compared with mobile GPU and desktop GPU. Finally, we will discuss the possibilities and trends of adopting emerging NVM technology for efficient learning systems to further improve the energy efficiency.

Biography
Yu Wang received his B.S. degree in 2002 and Ph.D. degree (with honor) in 2007 from Tsinghua University, Beijing. He is currently a tenured Associate Professor with the Department of Electronic Engineering, Tsinghua University. His research interests include brain inspired computing, application specific hardware computing, parallel circuit analysis, and power/reliability aware system design methodology. Dr. Wang has authored and coauthored over 170 papers in refereed journals and conferences. He has received Best Paper Award in FPGA 2017, ISVLSI 2012, and Best Poster Award in HEART 2012 with 8 Best Paper Nominations. He is a recipient of IBM X10 Faculty Award in 2010. He served as TPC chair for ICFPT 2011, Finance Chair of ISLPED 2012-2016, DATE 2017-18 Track Chair, and served as program committee member for leading conferences in these areas, including top EDA conferences such as DAC, DATE, ICCAD, ASP-DAC, and top FPGA conferences such as FPGA and FPT. Currently he serves as Co-Editor-in-Chief for ACM SIGDA E-Newsletter, Special Issue Editor for Elsevier Microelectronic Journal, Associate Editor for IEEE Transactions on CAD, and Journal of Circuits, Systems, and Computers. He also serves as guest editor for Integration, the VLSI Journal and IEEE Transactions on Multi-Scale Computing Systems. He has given 25+ invited talks in industry/academia. He is now with ACM Distinguished Speaker Program. He is an ACM/IEEE Senior Member.

联系人:杨帆
 
 
 
 

 

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