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虞志益:博士、副研究员

复旦大学引进人才

ASSCC 2009 Sub-Committee TPC Member

ASCON 2009 TPC Member

Email: zhiyiyu@fudan.edu.cn

Phone: 021-51355213

 

 

虞志益于2000年和2003年获复旦大学电子工程系(现微电子学系)学士和硕士,2007年获美国加州大学戴维斯分校(UC Davis)电子与计算机工程系博士。2007年至2008年任职于美国IntellaSys公司。他于2008年底作为复旦大学引进人才成为复旦微电子研究院副研究员。

他的研究兴趣包括高性能、低功耗的数字集成电路设计,以及多核处理器设计。在读博期间,他负责设计了被广泛认可为国际首个采用全局异步局部同步时钟的36核处理器 (AsAP),此项目被著名杂志EE TIMES 报道;他还参与设计了一167核处理器。在IntellaSys期间,他参与设计采用堆栈式架构的极小面积极低功耗的40核及144核处理器(SEAforth)。他已出版一本专著,发表(录用)论文20余篇,包括国际顶级的会议/期刊如:ISSCC, VLSI Symposium, 2JSSC, 3TVLSI, IEEE Micro,其中06年的ISSCC论文已被引用30余次。另外他已申请1份专利。

他是2009 ASSCC国际会议SOC组技术委员会成员,2009 ASICON国际会议技术委员会成员,及2009全国大学生电子设计竞赛上海赛区评审专家。

 

Zhiyi Yu received the B.S. and M.S. degrees in electrical engineering from Fudan University, Shanghai, China, in 2000 and 2003, respectively, and the Ph.D. degree in electrical and computer engineering from the University of California, Davis in 2007.

Dr. Yu is currently an Associate Professor with the State Key Laboratory of ASIC & System, Microelectronics Department, Fudan University, Shanghai, China. His research interests include high-performance and energy-efficient digital VLSI design with an emphasis on many-core processors. From 2007 to 2008, he was with IntellaSys Corporation, CA, USA, where he participated in the design of the many-core SEAForth chips which utilize stack-based processors with extremely small area and low power consumption. When in UC Davis, he was a key designer of the 36-core Asynchronous Array of simple Processors (AsAP) chip, and one of the designers of the 167-core second generation computational array chip. He has published 1 book and over 20 papers.

 

He serves as a member of the Technical Program sub-Committee of the IEEE Asian Solid-State Circuits Conference (ASSCC) in 2009, and a member of the TPC of the IEEE International Conference on ASIC in 2009.

Books:

  1. Zhiyi Yu, Bevan Baas, “High Performance and Energy Efficient Many-core DSP Systems”, VDM Verlag Dr. Müller Publisher, 2009

 

Papers (part):

  1. Zhiyi Yu, Bevan Baas, “A Low-Area Multi-link Interconnect Architecture for GALS Chip Multiprocessor”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), in press.
  2. Dean Truong, Wayne Cheng, Tinoosh Mohsenin, Zhiyi Yu, Toney Jacobson, Gouri Landge, Michael Meeuwsen, Christine Watnik, Anh Tran, Zhibin Xiao, Eric Work, Jeremy Webb, Paul Mejia, Bevan Baas, “A 167-processor Computational Platform in 65 nm CMOS”, IEEE Journal of Solid-State Circuits (JSSC), vol. 44, No. 4, pp. 1130-1144, April 2009.
  3. Zhiyi Yu, Bevan Baas, “High Performance, Energy Efficiency, and Scalability with GALS Chip Multiprocessors”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 17, Issue 1, pp. 66-79, Jan. 2009.
  4. Dean Truong, Wayne Cheng, Tinoosh Mohsenin, Zhiyi Yu, Toney Jacobson, Gouri Landge, Michael Meeuwsen, Christine Watnik, Paul Mejia, Anh Tran, Jeremy Webb, Eric Work, Zhibin Xiao, Bevan Baas, “A 167-processor 65 nm Computational Platform with Per-Processor Dynamic Supply Voltage and Dynamic Clock Frequency Scaling”, in IEEE Symposium on VLSI Circuits, June 2008, pp. 22-23.
  5. Zhiyi Yu, Michael Meeuwsen, Ryan Apperson, Omar Sattari, Michael Lai, Jeremy Webb, Eric Work, Dean Truong, Tinoosh Mohsenin, Bevan Baas, “AsAP: An Asynchronous Array of Simple Processors”, IEEE Journal of Solid-State Circuits (JSSC), Vol. 43, No. 3, pp. 695-705, March 2008.
  6. Ryan Apperson, Zhiyi Yu, Michael Meeuwsen, Tinoosh Mohsenin, Bevan Baas, “A Scalable Dual-Clock FIFO for Data Transfers between Arbitrary and Haltable Clock Domains”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 15, No. 10, pp. 1125-1134, October 2007.
  7. Bevan Baas, Zhiyi Yu, Michael Meeuwsen, Omar Sattari, Ryan Apperson, Eric Work, Jeremy Webb, Michael Lai, Tinoosh Mohsenin, Dean Truong, Jason Cheung, “AsAP: A Fine-grained Multi-core Platform for DSP Applications”, IEEE Micro, Vol. 27, No. 2, pp:34-45, March-April 2007.
  8. Zhiyi Yu, Michael Meeuwsen, Ryan Apperson, Omar Sattari, Michael Lai, Jeremy Webb, Eric Work, Tinoosh Mohsenin, Mandeep Singh, Bevan Baas, “An Asynchronous Array of Simple Processors for DSP Applications”, in IEEE International Solid-State Circuits Conference (ISSCC), February 2006, pp:428-429.

Address:

上海张衡路825号复旦大学微电子学系专用集成电路与系统国家重点实验室(201203

State-Key Laboratory of ASIC and System, Fudan University, 825 Zhangheng Road, Shanghai 201203 China

 

 
 
 
 

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